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NOIH2SM1000A
FREQUENTLY ASKED QUESTIONS
Question:
In the HAS2 data sheet, the pixel readout timing diagram
lacks information. It appears SYNC_X should change on the
rising edge of CLK_X. While SYNC_X is high, a rising
edge of CLK_X should sync XRD to X1 register. But the
diagram shows SYNC_X high for two CLK_X periods. Due
Answer:
CLK_X is divided internally in the sensor. SYNC_X is
based upon this divided clock. When SYNC_X is high for
an even pair of this divided clock cycles, the XRD is pushed
the length of this even pair of clock cycles. Though, when
SYNC_X drops during an uneven pair of divided clock
cycles, it is unclear what XRD will do. But this behavior is
most unlikely.
Question:
RES_REGn does not have any timing information. It is
the asynchronous reset for internal registers. How long must
it be held low?
Answer:
To be on the safe side, keep it low for at least 1 s. You
can apply the following sequence when powering up the
sensor:
? Power on device with known register settings
? During power on, keep RES_REGn low for at least 1 m s
? Apply line/column address upload timing diagram
Question:
The ADC serial interface timing diagram is incomplete. It
appears the SPI_DATA is supposed to change on the falling
edge of SPI_CLK. If so, then what is the setup and hold times
of the SPI_DATA around the rising edge of SPI_CLK? The
to timing variations, SYNC_X can be high for as many as
three different rising edges of CLK_X! The timing diagram
does not show any setup or hold timing for SYNC_X and
CLK_X.
SPI_CLK has a period of 1000 ns, so the SPI_DATA is
present for 500 ns prior to the rising edge of SPI_CLK. But
what is the SPI_DATA setup time for the *first* rising edge
of SPI_CLK (first bit of data)?
Answer:
The best way to operate the device is to change your SPI
data during the falling edge of the SPI clock. This gives you
plenty of time before the data is being sampled on the rising
edge of the SPI clock.
Consider a 100 ns hold and setup time of the SPI data
around the rising edge of the SPI clock. For the first rising
edge, consider a 500 ns setup time for the SPI data.
Question:
I noticed that BLANK remains high for the destructive
readout timing diagram even during the reset of YRST row.
However, in the nondestructive readout timing diagram,
BLANK is shown going low between a reset and line
selection, with no timing information.
What should the timing be? Or should it be left BLANK
constantly high during a line reset and subsequent line
selection during nondestructive readout?
Answer:
For the nondestructive read out, extend T1 and reduce T4.
This means that you can leave the BLANK signal high.
http://onsemi.com
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